#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
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#
bd22bde9 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
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#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5bcb4b8f |
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26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
41820c4b |
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26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
4aa05f6c |
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26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
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#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
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#
bd22bde9 |
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10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
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#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
c05ed00a |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
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#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
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#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
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#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
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#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
0e407c74 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
net: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
abdbfad2 |
|
19-Mar-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
net: phy: mv88e61xx: Convert to U_BOOT_PHY_DRIVER() Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
bd22bde9 |
|
10-Jan-2023 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move the comment from code to the help to explain what this does. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c05ed00a |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
5bcb4b8f |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: register phy_driver struct for 88E6071 Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
41820c4b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071 On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
4aa05f6c |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: add CPU port parameter init for 88E6071 On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
f41a722b |
|
26-Oct-2019 |
Anatolij Gustschin <agust@denx.de> |
net: phy: mv88e61xx: rework to enable detection of 88E6071 devices Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
69280961 |
|
04-Feb-2019 |
Tim Harvey <tharvey@gateworks.com> |
net: mv88e61xx: fix autonegotiation on ports phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
#
3cb51dad |
|
02-Jun-2018 |
Chris Packham <judge.packham@gmail.com> |
net: phy: mv88e61xx: Force CPU port link up When connecting to from a CPU direct to a 88e6097 typically RGMII is used. In order for traffic to actually pass we need to force the link up so the CPU MAC on the other end will see the link. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
4201223d |
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08-May-2017 |
Tom Rini <trini@konsulko.com> |
net: phy: mv88e61xx: Fix uninitialized variable warning The variable 'res' may be unused uninitialized if our call to mv88e61xx_port_read (register read) fails and we goto the error handling section. In this case we set 'res' to -EIO to indicate why we failed. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chris Packham <judge.packham@gmail.com> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
b755abec |
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25-Aug-2016 |
Chris Packham <judge.packham@gmail.com> |
net: mv88e61xx: Add support for fixed links On some boards these switches are wired directly into a SERDES interface on another Ethernet MAC. Add the ability to specify these kinds of boards using CONFIG_MV88E61XX_FIXED_PORTS which defines a bit mask of these fixed ports. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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#
65d4d00a |
|
25-Aug-2016 |
Chris Packham <judge.packham@gmail.com> |
net: Add support for mv88e609x switches The Marvell Link Street mv88e60xx is a series of FastEthernet switch chips, some of which also support Gigabit ports. It is similar to the mv88e61xx series which support Gigabit on all ports. The main difference is the number of ports. Which affects the PORT_COUNT define and the size of the mask passed to mv88e61xx_port_set_vlan(). Other than that it's just a matter of adding the appropriate chip IDs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Cc: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
24ae3961 |
|
31-Mar-2016 |
Kevin Smith <kevin.smith@elecsyscorp.com> |
net: phy: Add PHY driver for mv88e61xx switches The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
83c05515 |
|
31-Mar-2016 |
Kevin Smith <kevin.smith@elecsyscorp.com> |
net: Remove unused mv88e61xx switch driver No boards are using this driver. Remove in preparation for a new driver with integrated PHY support. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
|
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
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#
0a16ea59 |
|
26-Nov-2012 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
mv88e61xx: refactor PHY and SWITCH level-code Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
|
#
8ef583a0 |
|
23-Dec-2010 |
Mike Frysinger <vapier@gentoo.org> |
miiphy: convert to linux/mii.h The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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#
32e7f239 |
|
21-Sep-2009 |
Prafulla Wadaskar <prafulla@marvell.com> |
net: phy: mv88e61xx.c : fixed build warning following build warning was observed mv88e61xx.c: In function ‘mv88e61xx_busychk’: mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules This patch fixes the same Patch tested for rd6281a board build Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
|
#
08c2df33 |
|
10-Aug-2009 |
Prafulla Wadaskar <prafulla@marvell.com> |
net: phy: bugfixes: mv88E61xx compiler warnings fixed 1. mv88E61xx driver compiler warnings fixed 2. idstr if-else statements changed to switch() construct and added default case too. This fixed idstr may be uninitialized warning Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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443ce4ac |
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16-Jul-2009 |
Prafulla Wadaskar <prafulla@marvell.com> |
net: phy: bugfixes: mv88E61xx multichip addressing support With these fixes, this driver works properly for multi chip addressging mode Bugfixes: 1. Build error fixed for function mv88e61xx_busychk_multic-fixed 2. PHY dev address error detection- fixed 3. wrong busy bit was refered in function mv88e61xx_busychk -fixed 4. invalid data read ptr was refered for RD_PHY in case of multichip addressing mode -fixed The Multichip Address mode is tested with RD6281A board having MV88E6165 switch on it Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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6f51deb7 |
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18-May-2009 |
Prafulla Wadaskar <prafulla@marvell.com> |
Marvell MV88E61XX Switch Driver support Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported for:- default or router port vlan configuration led_init configuration mdip/n polarity reversal configuration Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam@marvell.com> Michael Blostein <michaelbl@marvell.com Reviewed by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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