History log of /u-boot/drivers/clk/altera/clk-agilex.c
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# d678a59d 18-May-2024 Tom Rini <trini@konsulko.com>

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 92bb2cd4 01-May-2024 Tom Rini <trini@konsulko.com>

clk: Remove <common.h> and add needed includes

Remove <common.h> from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 401d1c4f 30-Oct-2020 Simon Glass <sjg@chromium.org>

common: Drop asm/global_data.h from common header

Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 8a8d24bd 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename ..._platdata variables to just ..._plat

Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# d1998a9f 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename ofdata_to_platdata() to of_to_plat()

This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c69cda25 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename dev_get_platdata() to dev_get_plat()

Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# caa4daa2 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename 'platdata' variables to just 'plat'

We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# 41575d8e 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename auto_alloc_size members to be shorter

This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# d24f2bc1 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Additional membus writes for HPS PLL

Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 35d847ed 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Handle clock configuration differently in SPL and U-Boot proper

Since warm reset may optionally set the CLock Manager to'boot mode',
the clock driver should always force the Agilex's Clock Manager to
'boot mode' before the clock driver start configuring the Clock Manager
in SPL.
In SSBL, clock driver will skip the Clock Manager configuration
if it's already being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# d3e829b6 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock enable support

Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 36162a8e 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add NAND clock support

Add get nand_clk and nand_x clock support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 2548493a 16-Jul-2020 Masahiro Yamada <masahiroy@kernel.org>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 7208396b 24-Jul-2020 Tom Rini <trini@konsulko.com>

Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"

This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to 56d37f1c564107e27d873181d838571b7d7860e7.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 60e7fa8b 16-Jul-2020 Masahiro Yamada <masahiroy@kernel.org>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# cd93d625 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# f7ae49fc 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop log.h from common header

Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c168fc71 27-Nov-2019 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 92bb2cd4 01-May-2024 Tom Rini <trini@konsulko.com>

clk: Remove <common.h> and add needed includes

Remove <common.h> from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 401d1c4f 30-Oct-2020 Simon Glass <sjg@chromium.org>

common: Drop asm/global_data.h from common header

Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 8a8d24bd 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename ..._platdata variables to just ..._plat

Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# d1998a9f 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename ofdata_to_platdata() to of_to_plat()

This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c69cda25 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename dev_get_platdata() to dev_get_plat()

Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# caa4daa2 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename 'platdata' variables to just 'plat'

We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# 41575d8e 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename auto_alloc_size members to be shorter

This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# d24f2bc1 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Additional membus writes for HPS PLL

Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 35d847ed 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Handle clock configuration differently in SPL and U-Boot proper

Since warm reset may optionally set the CLock Manager to'boot mode',
the clock driver should always force the Agilex's Clock Manager to
'boot mode' before the clock driver start configuring the Clock Manager
in SPL.
In SSBL, clock driver will skip the Clock Manager configuration
if it's already being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# d3e829b6 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock enable support

Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 36162a8e 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add NAND clock support

Add get nand_clk and nand_x clock support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 2548493a 16-Jul-2020 Masahiro Yamada <masahiroy@kernel.org>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 7208396b 24-Jul-2020 Tom Rini <trini@konsulko.com>

Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"

This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to 56d37f1c564107e27d873181d838571b7d7860e7.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 60e7fa8b 16-Jul-2020 Masahiro Yamada <masahiroy@kernel.org>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# cd93d625 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# f7ae49fc 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop log.h from common header

Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c168fc71 27-Nov-2019 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 401d1c4f 30-Oct-2020 Simon Glass <sjg@chromium.org>

common: Drop asm/global_data.h from common header

Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 8a8d24bd 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename ..._platdata variables to just ..._plat

Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# d1998a9f 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename ofdata_to_platdata() to of_to_plat()

This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c69cda25 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename dev_get_platdata() to dev_get_plat()

Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# caa4daa2 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename 'platdata' variables to just 'plat'

We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# 41575d8e 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename auto_alloc_size members to be shorter

This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# d24f2bc1 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Additional membus writes for HPS PLL

Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 35d847ed 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Handle clock configuration differently in SPL and U-Boot proper

Since warm reset may optionally set the CLock Manager to'boot mode',
the clock driver should always force the Agilex's Clock Manager to
'boot mode' before the clock driver start configuring the Clock Manager
in SPL.
In SSBL, clock driver will skip the Clock Manager configuration
if it's already being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# d3e829b6 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock enable support

Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 36162a8e 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add NAND clock support

Add get nand_clk and nand_x clock support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 2548493a 16-Jul-2020 Masahiro Yamada <yamada.masahiro@socionext.com>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 7208396b 24-Jul-2020 Tom Rini <trini@konsulko.com>

Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"

This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to 56d37f1c564107e27d873181d838571b7d7860e7.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 60e7fa8b 16-Jul-2020 Masahiro Yamada <yamada.masahiro@socionext.com>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# cd93d625 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# f7ae49fc 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop log.h from common header

Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c168fc71 27-Nov-2019 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 8a8d24bd 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename ..._platdata variables to just ..._plat

Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# d1998a9f 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename ofdata_to_platdata() to of_to_plat()

This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c69cda25 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename dev_get_platdata() to dev_get_plat()

Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# caa4daa2 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename 'platdata' variables to just 'plat'

We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# 41575d8e 03-Dec-2020 Simon Glass <sjg@chromium.org>

dm: treewide: Rename auto_alloc_size members to be shorter

This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# d24f2bc1 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Additional membus writes for HPS PLL

Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 35d847ed 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Handle clock configuration differently in SPL and U-Boot proper

Since warm reset may optionally set the CLock Manager to'boot mode',
the clock driver should always force the Agilex's Clock Manager to
'boot mode' before the clock driver start configuring the Clock Manager
in SPL.
In SSBL, clock driver will skip the Clock Manager configuration
if it's already being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# d3e829b6 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock enable support

Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 36162a8e 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add NAND clock support

Add get nand_clk and nand_x clock support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 2548493a 16-Jul-2020 Masahiro Yamada <yamada.masahiro@socionext.com>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 7208396b 24-Jul-2020 Tom Rini <trini@konsulko.com>

Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"

This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to 56d37f1c564107e27d873181d838571b7d7860e7.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 60e7fa8b 16-Jul-2020 Masahiro Yamada <yamada.masahiro@socionext.com>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# cd93d625 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# f7ae49fc 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop log.h from common header

Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c168fc71 27-Nov-2019 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# d24f2bc1 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Additional membus writes for HPS PLL

Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 35d847ed 10-Jul-2020 Chee Hong Ang <chee.hong.ang@intel.com>

clk: agilex: Handle clock configuration differently in SPL and U-Boot proper

Since warm reset may optionally set the CLock Manager to'boot mode',
the clock driver should always force the Agilex's Clock Manager to
'boot mode' before the clock driver start configuring the Clock Manager
in SPL.
In SSBL, clock driver will skip the Clock Manager configuration
if it's already being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# d3e829b6 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock enable support

Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 36162a8e 10-Jul-2020 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add NAND clock support

Add get nand_clk and nand_x clock support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 2548493a 16-Jul-2020 Masahiro Yamada <yamada.masahiro@socionext.com>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 7208396b 24-Jul-2020 Tom Rini <trini@konsulko.com>

Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"

This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to 56d37f1c564107e27d873181d838571b7d7860e7.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 60e7fa8b 16-Jul-2020 Masahiro Yamada <yamada.masahiro@socionext.com>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# cd93d625 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# f7ae49fc 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop log.h from common header

Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c168fc71 27-Nov-2019 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 2548493a 16-Jul-2020 Masahiro Yamada <yamada.masahiro@socionext.com>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 7208396b 24-Jul-2020 Tom Rini <trini@konsulko.com>

Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"

This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to 56d37f1c564107e27d873181d838571b7d7860e7.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 60e7fa8b 16-Jul-2020 Masahiro Yamada <yamada.masahiro@socionext.com>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# cd93d625 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# f7ae49fc 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop log.h from common header

Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c168fc71 27-Nov-2019 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 7208396b 24-Jul-2020 Tom Rini <trini@konsulko.com>

Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"

This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing
changes made to 56d37f1c564107e27d873181d838571b7d7860e7.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# 60e7fa8b 16-Jul-2020 Masahiro Yamada <yamada.masahiro@socionext.com>

treewide: convert devfdt_get_addr() to dev_read_addr()

When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# cd93d625 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# f7ae49fc 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop log.h from common header

Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c168fc71 27-Nov-2019 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# cd93d625 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# f7ae49fc 10-May-2020 Simon Glass <sjg@chromium.org>

common: Drop log.h from common header

Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>


/u-boot/drivers/clk/altera/clk-agilex.c
# c168fc71 27-Nov-2019 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>


/u-boot/drivers/clk/altera/clk-agilex.c
# c168fc71 27-Nov-2019 Ley Foon Tan <ley.foon.tan@intel.com>

clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>


/u-boot/drivers/clk/altera/clk-agilex.c