#
448e2b63 |
|
16-Jan-2023 |
Tom Rini <trini@konsulko.com> |
event: Correct dependencies on the EVENT framework The event framework is just that, a framework. Enabling it by itself does nothing, so we shouldn't ask the user about it. Reword (and correct typos) around this the option and help text. This also applies to DM_EVENT and EVENT_DYNAMIC. Only EVENT_DEBUG and CMD_EVENT should be visible to the user to select, when EVENT is selected. With this, it's time to address the larger problems. When functionality uses events, typically via EVENT_SPY, the appropriate framework then must be select'd and NOT imply'd. As the functionality will cease to work (and so, platforms will fail to boot) this is non-optional and where select is appropriate. Audit the current users of EVENT_SPY to have a more fine-grained approach to select'ing the framework where used. Also ensure the current users of event_register and also select EVENT_DYNAMIC. Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Reported-by: Oliver Graute <Oliver.Graute@kococonnector.com> Reported-by: Francesco Dolcini <francesco.dolcini@toradex.com> Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Fixes: 42fdcebf859f ("event: Convert misc_init_f() to use events") Fixes: c5ef2025579e ("dm: fix DM_EVENT dependencies") Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Fabio Estevam <festevam@denx.de> |
#
b4c2c151 |
|
27-Aug-2021 |
Michal Simek <michal.simek@amd.com> |
Kconfig: Remove all default n/no options default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6744c0d6 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
sound: x86: link: Add sound support Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fcfc8a82 |
|
10-Jun-2018 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Conditionally build the pinctrl_ich6 driver The pinctrl_ich6 driver is currently unconditionally built for all x86 boards. Let's use a Kconfig option to control the build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b173b4ea |
|
03-Jun-2018 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Imply USB_XHCI_HCD The Panther Point chipset connected to Ivybridge has xHC integrated, imply it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9fd95ef0 |
|
08-Dec-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
ata: Migrate CONFIG_SCSI_AHCI to Kconfig And use 'imply' liberally. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
#
c1c3fe23 |
|
03-Aug-2017 |
Simon Glass <sjg@chromium.org> |
env: Convert CONFIG_ENV_IS_IN... to a choice At present we support multiple environment drivers but there is not way to select between them at run time. Also settings related to the position and size of the environment area are global (i.e. apply to all locations). Until these limitations are removed we cannot really support more than one environment location. Adjust the location to be a choice so that only one can be selected. By default the environment is 'nowhere', meaning that the environment exists only in memory and cannot be saved. Also expand the help for the 'nowhere' option and move it to the top since it is the default. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Move all of the imply logic to default X if Y so it works again] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
24357dfd |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Switch all boards to use DM SCSI After MMC is converted to DM, convert to use DM SCSI as well for all x86 boards and imply BLK for both MMC and SCSI drivers. CONFIG_SCSI_DEV_LIST is no longer used. Clean them up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
72436892 |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert INTEL_ICH6_GPIO to Kconfig This converts Intel ICH6 GPIO driver to Kconfig, and add it to the imply list of platform drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b9342b2c |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Move USB to platform Kconfig Like other peripheral drivers, move USB related drivers to platform Kconfig as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a5b21294 |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: kconfig: Imply platform specific drivers Imply drivers that are working with Ivybridge platform in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
67f99f97 |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Imply ENABLE_MRC_CACHE in the platform Kconfig Platform knows whether MRC cache is implemented, but using it can be a choice of a specific board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1e452b46 |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Imply HAVE_INTEL_ME in the platform Kconfig Intel Management Engine is required by the platform, however it's not a must have when building a U-Boot image. For example, during development normally programming ME firmware is a one-time effort. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7d35bc1 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common MRC Kconfig options to the common file At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a2e3b05e |
|
17-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
43741396 |
|
17-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Add FSP support IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org> |
#
fa331fad |
|
11-Dec-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Do not require HAVE_INTEL_ME Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
d475d590 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove CPU_INTEL_SOCKET_RPGA989 This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
efe2d80c |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Clean up ivybridge/chrome Kconfig options There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
9bf76c21 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
946c2b52 |
|
16-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS Ivybridge is not ready for U-Boot MP initialization yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
380ab5cc |
|
19-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop the Kconfig MRC cache information This is now stored in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
65dd74a6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Implement SDRAM init Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
b4c2c151 |
|
27-Aug-2021 |
Michal Simek <michal.simek@xilinx.com> |
Kconfig: Remove all default n/no options default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6744c0d6 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
sound: x86: link: Add sound support Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fcfc8a82 |
|
10-Jun-2018 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Conditionally build the pinctrl_ich6 driver The pinctrl_ich6 driver is currently unconditionally built for all x86 boards. Let's use a Kconfig option to control the build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b173b4ea |
|
03-Jun-2018 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Imply USB_XHCI_HCD The Panther Point chipset connected to Ivybridge has xHC integrated, imply it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
9fd95ef0 |
|
08-Dec-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
ata: Migrate CONFIG_SCSI_AHCI to Kconfig And use 'imply' liberally. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
#
c1c3fe23 |
|
03-Aug-2017 |
Simon Glass <sjg@chromium.org> |
env: Convert CONFIG_ENV_IS_IN... to a choice At present we support multiple environment drivers but there is not way to select between them at run time. Also settings related to the position and size of the environment area are global (i.e. apply to all locations). Until these limitations are removed we cannot really support more than one environment location. Adjust the location to be a choice so that only one can be selected. By default the environment is 'nowhere', meaning that the environment exists only in memory and cannot be saved. Also expand the help for the 'nowhere' option and move it to the top since it is the default. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Move all of the imply logic to default X if Y so it works again] Signed-off-by: Tom Rini <trini@konsulko.com> |
#
24357dfd |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Switch all boards to use DM SCSI After MMC is converted to DM, convert to use DM SCSI as well for all x86 boards and imply BLK for both MMC and SCSI drivers. CONFIG_SCSI_DEV_LIST is no longer used. Clean them up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
72436892 |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert INTEL_ICH6_GPIO to Kconfig This converts Intel ICH6 GPIO driver to Kconfig, and add it to the imply list of platform drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b9342b2c |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Move USB to platform Kconfig Like other peripheral drivers, move USB related drivers to platform Kconfig as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a5b21294 |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: kconfig: Imply platform specific drivers Imply drivers that are working with Ivybridge platform in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
67f99f97 |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Imply ENABLE_MRC_CACHE in the platform Kconfig Platform knows whether MRC cache is implemented, but using it can be a choice of a specific board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1e452b46 |
|
30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Imply HAVE_INTEL_ME in the platform Kconfig Intel Management Engine is required by the platform, however it's not a must have when building a U-Boot image. For example, during development normally programming ME firmware is a one-time effort. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
f7d35bc1 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common MRC Kconfig options to the common file At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a2e3b05e |
|
17-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
43741396 |
|
17-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Add FSP support IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org> |
#
fa331fad |
|
11-Dec-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Do not require HAVE_INTEL_ME Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
d475d590 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove CPU_INTEL_SOCKET_RPGA989 This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
efe2d80c |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Clean up ivybridge/chrome Kconfig options There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
9bf76c21 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
946c2b52 |
|
16-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS Ivybridge is not ready for U-Boot MP initialization yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
380ab5cc |
|
19-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop the Kconfig MRC cache information This is now stored in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
65dd74a6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Implement SDRAM init Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6744c0d6 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
sound: x86: link: Add sound support Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fcfc8a82 |
|
10-Jun-2018 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Conditionally build the pinctrl_ich6 driver The pinctrl_ich6 driver is currently unconditionally built for all x86 boards. Let's use a Kconfig option to control the build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b173b4ea |
|
03-Jun-2018 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Imply USB_XHCI_HCD The Panther Point chipset connected to Ivybridge has xHC integrated, imply it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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9fd95ef0 |
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08-Dec-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
ata: Migrate CONFIG_SCSI_AHCI to Kconfig And use 'imply' liberally. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
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c1c3fe23 |
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03-Aug-2017 |
Simon Glass <sjg@chromium.org> |
env: Convert CONFIG_ENV_IS_IN... to a choice At present we support multiple environment drivers but there is not way to select between them at run time. Also settings related to the position and size of the environment area are global (i.e. apply to all locations). Until these limitations are removed we cannot really support more than one environment location. Adjust the location to be a choice so that only one can be selected. By default the environment is 'nowhere', meaning that the environment exists only in memory and cannot be saved. Also expand the help for the 'nowhere' option and move it to the top since it is the default. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Move all of the imply logic to default X if Y so it works again] Signed-off-by: Tom Rini <trini@konsulko.com> |
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24357dfd |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Switch all boards to use DM SCSI After MMC is converted to DM, convert to use DM SCSI as well for all x86 boards and imply BLK for both MMC and SCSI drivers. CONFIG_SCSI_DEV_LIST is no longer used. Clean them up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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72436892 |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert INTEL_ICH6_GPIO to Kconfig This converts Intel ICH6 GPIO driver to Kconfig, and add it to the imply list of platform drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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b9342b2c |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Move USB to platform Kconfig Like other peripheral drivers, move USB related drivers to platform Kconfig as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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a5b21294 |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: kconfig: Imply platform specific drivers Imply drivers that are working with Ivybridge platform in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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67f99f97 |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Imply ENABLE_MRC_CACHE in the platform Kconfig Platform knows whether MRC cache is implemented, but using it can be a choice of a specific board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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1e452b46 |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Imply HAVE_INTEL_ME in the platform Kconfig Intel Management Engine is required by the platform, however it's not a must have when building a U-Boot image. For example, during development normally programming ME firmware is a one-time effort. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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f7d35bc1 |
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11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common MRC Kconfig options to the common file At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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a2e3b05e |
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17-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
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43741396 |
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17-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Add FSP support IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org> |
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fa331fad |
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11-Dec-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Do not require HAVE_INTEL_ME Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
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d475d590 |
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25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove CPU_INTEL_SOCKET_RPGA989 This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
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efe2d80c |
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25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Clean up ivybridge/chrome Kconfig options There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
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9bf76c21 |
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25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
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946c2b52 |
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16-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS Ivybridge is not ready for U-Boot MP initialization yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
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380ab5cc |
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19-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop the Kconfig MRC cache information This is now stored in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> |
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65dd74a6 |
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12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Implement SDRAM init Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org> |
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8ef07571 |
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12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
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fcfc8a82 |
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10-Jun-2018 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Conditionally build the pinctrl_ich6 driver The pinctrl_ich6 driver is currently unconditionally built for all x86 boards. Let's use a Kconfig option to control the build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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b173b4ea |
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03-Jun-2018 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Imply USB_XHCI_HCD The Panther Point chipset connected to Ivybridge has xHC integrated, imply it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
9fd95ef0 |
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08-Dec-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
ata: Migrate CONFIG_SCSI_AHCI to Kconfig And use 'imply' liberally. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
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#
c1c3fe23 |
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03-Aug-2017 |
Simon Glass <sjg@chromium.org> |
env: Convert CONFIG_ENV_IS_IN... to a choice At present we support multiple environment drivers but there is not way to select between them at run time. Also settings related to the position and size of the environment area are global (i.e. apply to all locations). Until these limitations are removed we cannot really support more than one environment location. Adjust the location to be a choice so that only one can be selected. By default the environment is 'nowhere', meaning that the environment exists only in memory and cannot be saved. Also expand the help for the 'nowhere' option and move it to the top since it is the default. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Move all of the imply logic to default X if Y so it works again] Signed-off-by: Tom Rini <trini@konsulko.com>
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24357dfd |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Switch all boards to use DM SCSI After MMC is converted to DM, convert to use DM SCSI as well for all x86 boards and imply BLK for both MMC and SCSI drivers. CONFIG_SCSI_DEV_LIST is no longer used. Clean them up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
72436892 |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert INTEL_ICH6_GPIO to Kconfig This converts Intel ICH6 GPIO driver to Kconfig, and add it to the imply list of platform drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
b9342b2c |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Move USB to platform Kconfig Like other peripheral drivers, move USB related drivers to platform Kconfig as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
a5b21294 |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: kconfig: Imply platform specific drivers Imply drivers that are working with Ivybridge platform in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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67f99f97 |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Imply ENABLE_MRC_CACHE in the platform Kconfig Platform knows whether MRC cache is implemented, but using it can be a choice of a specific board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
1e452b46 |
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30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Imply HAVE_INTEL_ME in the platform Kconfig Intel Management Engine is required by the platform, however it's not a must have when building a U-Boot image. For example, during development normally programming ME firmware is a one-time effort. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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#
f7d35bc1 |
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11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common MRC Kconfig options to the common file At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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#
a2e3b05e |
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17-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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#
43741396 |
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17-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Add FSP support IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
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#
fa331fad |
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11-Dec-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Do not require HAVE_INTEL_ME Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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#
d475d590 |
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25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove CPU_INTEL_SOCKET_RPGA989 This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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#
efe2d80c |
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25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Clean up ivybridge/chrome Kconfig options There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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9bf76c21 |
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25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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#
946c2b52 |
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16-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS Ivybridge is not ready for U-Boot MP initialization yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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#
380ab5cc |
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19-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop the Kconfig MRC cache information This is now stored in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
65dd74a6 |
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12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Implement SDRAM init Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
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#
8ef07571 |
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12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
|