#
0b9441ae |
|
12-Oct-2023 |
Tom Rini <trini@konsulko.com> |
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io> |
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com> |
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
40686c39 |
|
24-Jun-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Clean up IPI initialization code The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f295e00c |
|
06-Mar-2020 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Avoid calling sbi_clear_ipi() There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b3e97ba |
|
08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
8b3e97ba |
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08-Dec-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: add functions for reading the IPI status Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f152febb |
|
17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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#
f152febb |
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17-Mar-2019 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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